Introduction
This project's goal is the production of a printed circuit board to facilitate the rapid prototyping of digital systems via programmable logic. The board under development is depicted below. It can be operated in a standalone mode or as a PCI bus plugin to a Windows or Linux-based host computer.
The board features a Xilinx XCV1000 FPGA, part of the so-called Virtex family of large programmable logic chips. This FPGA contains more than 25000 CLBs and represents the equivalent of more than 1,000,000 logic gates. Also on-board is a 32 Mbyte SDRAM and mezzanine-style connectors supporting add-on peripheral boards containing such things as audio/video interfaces, A/D and D/A convertors and the like. The FPGA can be configured to operate as a special-purpose digital system with access to the SDRAM and analog channels. Alternatively it can be configured to operate in a cooperative way, coordinating its processing with that of an on-board TMS320C6205 DSP. This DSP was chosen in part because of its built-in PCI interface. It operates at 200 MHz and offers significant parallelism within its datapaths. It is our hope that ultimately this card can be configured to provide very high-quality compression and decompression for video conferencing and similar mixed-signal applications.
Current Projects
- JPEG Compression/Decompression Core .... (J. Rosenthal thesis)
- JPEG Codec on Virtex XCV1000 FPGA. The goal of this project is to alleviate burdensome processing overhead from the processor onto dedicated hardware. The hope is to provide Baseline JPEG Compression/Decompression for static images. If the throughput is significant, motion JPEG can be processed.
- "Pseudo-Synchronous" FIFO Core
- Using Virtex Block SRAMs, a FIFO is constructed to provide an interface between the DSP external memory interface and the FPGA. Using this core, data from the DSP can be synchronously introduced into the design. Advantages can be obtained in throughput for a pipelined design. This is a necessary feature for pipelines, or design which require data in successive clocks. The DSP external memory interface is 100 MHz and the FPGA core is running 25 MHz, thus, this FIFO will alleviate the burden of the "pseudo-synchronous" system.
- Using DSP BIOS
- This project entails using the Texas Instruments DSP/BIOS facilities to implement real-time embedded systems.